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experiment6
- VHDL课程实验6,数控分频器的设计。对应不同的输入信号,预置数(初始计数值)设定不同的值,计数器以此预置数为初始状态进行不同模值的计数,当计数器的状态全为1时,计数器输出溢出信号。用计数器的溢出信号作为输出信号或输出信号的控制值,使输出信号的频率受控于输入的预置数-VHDL course experiment 6, NC Divider. Corresponding to different input signals, the set value (initial count) to set
fpga
- vhdl和c编写,fpga结合单片机完成测频计的功能,fpga主要完成频率的测量并把数据发送给单片机,单片机控制12864液晶完成显示-vhdl and c preparation, fpga of the single chip to complete the function of frequency meter, fpga major to complete the measurement frequency and the data sent to the MCU, MCU contro
frequency25
- 频率分度计,测试信号频率,并将信号频率显示出来,利用VHDL语言编程实现-Frequency meter, the test signal frequency, and the frequency of the signal displayed using VHDL language programming
kebenchengxu
- VHDL代码,一些课本的小程序。包含3线-8线译码器,4选1选择器,6层电梯,8线-3线编码器,8线-3线优先编码器,8选1,BCD-7段显示译码器真值表,半加器,摩尔状态机,数字频率计,数字时钟,同步计数器,序列检测器的设计,序列信号发生器,一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3